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[VHDL-FPGA-Verilog] 8259

Description: 这是一个中断控制器的IP，功能很全，可以直接使用，类似于INTEL的8259，作为中断扩展。-This is an interrupt controller of the IP, is the whole function can be used directly, similar to INTEL in 8259, as extended interruption.
Platform: | Size: 2048 | Author: kristing | Hits:

[VHDL-FPGA-Verilog] elivator_control

Description: 电梯控制器 用于八层楼双电梯的协调调度 可进行扩展-Elevator controller for the eight-floor, two-elevator scheduling coordination can be extended
Platform: | Size: 544768 | Author: 王鹤 | Hits:

[VHDL-FPGA-Verilog] ZBT_SRAM

Description: ZBT（高速同步）SRAM控制器参考设计VHDL代码-ZBT (high-speed sync) SRAM controller reference design VHDL code
Platform: | Size: 9216 | Author: 李锐 | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[Windows Develop] TrafficLight

Description: 设计一个交通信号灯控制器，由一条主干道和一条支干道汇合成十字路口，在每个入口处设置红、绿、黄三色信号灯，红灯亮禁止通行，绿灯亮允许通行，黄灯亮则给行驶中的车辆有时间停在禁行线外。-The design of a traffic signal controller, by a trunk and a branch road汇合成crossroads at the entrance to set up in each red, green, yellow three-color lights, red light curfew, green permit passage to a yellow light while driving vehicles parked in the ban have time outside the lane.
Platform: | Size: 282624 | Author: zhuzi200803 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 基于FPGA的SDRAM控制器的设计和实现,还比较好勒.-FPGA-based SDRAM controller design and realization, but also better le.
Platform: | Size: 69632 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] frequency-phase_test_vhdl

Description: 相位差测试，频率测试、频率计数器、闸门控制器、显示译码控制的vhdl程序-Phase tests, the frequency of testing, frequency counters, gate controller, showing decoding control VHDL procedures
Platform: | Size: 5120 | Author: 王充 | Hits:

[Communication] CRC16_D8.v

Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] I2C_Verilog

Description: I2C 控制器的 Verilog源程序 example-I2C controller Verilog source code example
Platform: | Size: 206848 | Author: 展望 | Hits:

[VHDL-FPGA-Verilog] EDAdeisgn(2)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷2实例包括：多路彩灯控制器的设计与分析、智力抢器的设计与分析、微波炉控制器、数据采集控制系统、电梯控制器的设计与分析-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Volume 2 Examples include: multi-way lantern controller design and analysis, intelligence steal the design and analysis, microwave oven controller, data acquisition and control systems, elevator controller design and analysis
Platform: | Size: 4952064 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] can_parts

Description: 实现CAN控制器的VHDL源码,与大家分享.-Realize CAN controller VHDL source code to share with you.
Platform: | Size: 40960 | Author: fhomewl | Hits:

[Other] cnt6

Description: 数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。-Scanning digital tube display controller, also showed that six different 0,1,2,3,4,5 digital graphics to digital tube 6. Reset all digital tube body.
Platform: | Size: 351232 | Author: fishafish | Hits:

[Internet-Network] POC

Description: a parallel output controller(handshake protocol)-a parallel output controller (handshake protocol)
Platform: | Size: 4096 | Author: humengwei | Hits:

[VHDL-FPGA-Verilog] hdlc_vhdl

Description: This a VHDL implementation of an HDLC controller
Platform: | Size: 180224 | Author: | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Platform: | Size: 474112 | Author: 张宁 | Hits:

[VHDL-FPGA-Verilog] lcd_controler

Description: 用vhdl编写的lcd控制器，已经应用到了实际的生产中-Prepared using VHDL lcd controller, have been applied to practical production
Platform: | Size: 1024 | Author: 曾工 | Hits:

[VHDL-FPGA-Verilog] pd064vt5

Description: 用vhdl编写的lcd控制器，已经应用到了实际的生产中-Prepared using VHDL lcd controller, have been applied to practical production
Platform: | Size: 1024 | Author: 曾工 | Hits:
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